بررسی ساختارهای مختلف full adder

thesis
abstract

در این پایان نامه پارامترهای مهم در مدارات دیجیتال توضیح داده شده و چند سلول جمع کننده متداول مورد بررسی قرار گرفته است. ایده های مختلفی که در پیاده سازی مدارات جمع کننده وجود داشته، شبیه سازی شده است. در پیاده سازی مدار سلول جمع کننده، در بعضی از مقالات طبقات ورودی و در بعضی دیگر طبقات خروجی متفاوت است. در مقالات متفاوت از منطق های cmos مکمل، نسبتی، ترانزیستور عبوری مکمل، گیت های انتقال، تابع اکثریت استفاده شده است. همه مدارات جمع کننده پایان نامه توسط نرم افزار hspice در تکنولوژی cmos tsmc 0.18µm شبیه سازی کرده و به نتایج شبیه سازی مقالات رسیده ایم و مدارات را با هم مقایسه کرده ایم. ما طبـقه ورودی را تغییر داده، از منطق ترانزیستور عبوری استفاده کرده و شبیه سازی کرده ایم و به توان مصرفی، زمان تاخیر و درنتیجه pdp بهتری رسیدهایم. در دو جمع کننده طبقه خروجی cout را تغییر داده و بعد از شبیه سازی به نتایج بهتری رسیده ایم. به عنوان نمونه مداری را در گوشه های پروسس، ولتاژهای تغذیه متفاوت و گوشه های دمایی شبیه سازی کرده ایم.

First 15 pages

Signup for downloading 15 first pages

Already have an account?login

similar resources

Evolutionary QCA Fault-Tolerant Reversible Full Adder

Today, the use of CMOS technology for the manufacture of electronic ICs has faced many limitations. Many alternatives to CMOS technology are offered and made every day. Quantum-dot cellular automata (QCA) is one of the most widely used. QCA gates and circuits have many advantages including small size, low power consumption and high speed. On the other hand, using special digital gates called re...

full text

Performance evaluation of full adder

This paper presents different techniques of one bit Full adder. In every technique the main requirements are power consumption, speed and power delay product. The proposed FIN-FET technique gives the bette.r power consumption, speed and power delay product than other techniques. The proposed Fin-FET technique is compared with some of the popular adders based on the power consumption, speed and ...

full text

Full Adder Circuit . Part I

A set is pair if: (Def.1) There exist sets x, y such that it = 〈x, y〉. Let us mention that every set which is pair is also non empty. Let x, y be sets. Observe that 〈x, y〉 is pair. Let us mention that there exists a set which is pair and there exists a set which is non pair. Let us observe that every natural number is non pair. A set has a pair if: (Def.2) There exists a pair set x such that x ...

full text

Low Power Domino Full Adder

With the advancement of technology, power consumption and higher speed becomes major concern for VLSI systems. In this paper, a new hybrid domino XOR is proposed and compared with existing domino XOR cell. As an application of proposed XOR cell, 1-bit full adder has been designed and compared with a full adder circuit using existing XOR cell. Both proposed designs XOR and full adder show better...

full text

Full Adder Circuit. Part II

In this article we continue the investigations from [5] of verification of a design of adder circuit. We define it as a combination of 1-bit adders using schemes from [6]. n-bit adder circuit has the following structure 1st bit adder x 1 y 1 x 2 y 2 r 1 r 2 2nd bit adder nth bit adder x n y n r n As the main result we prove the stability of the circuit. Further works will consist of the proof o...

full text

Power Optimized Full Adder Architecture

In most of the digital systems the full-adders are the basic and the fundamental components. Due to the increase in number of transistors on the chip and its shrinkage has made the power consumption to be more. This power consumption is due to the flow of current and causes the battery life to be reduced. Hence the need of low power designs is the primary requirement in the VLSI field. The full...

full text

My Resources

Save resource for easier access later

Save to my library Already added to my library

{@ msg_add @}


document type: thesis

وزارت علوم، تحقیقات و فناوری - موسسه آموزش عالی غیرانتفاعی و غیردولتی سجاد مشهد - پژوهشکده برق

Hosted on Doprax cloud platform doprax.com

copyright © 2015-2023